Hardware Engineer, FPGA

Normal Computing is hiring a Hardware Engineer, FPGA to bring physics-inspired ASIC designs onto FPGA platforms for pre-silicon validation and early software development. The role also builds post-silicon bring-up and characterization test infrastructure, spanning platform selection, RTL implementation, lab debugging, and supporting software.

Responsibilities

• FPGA Platform Ownership: Lead the selection, procurement, and bring-up of FPGA prototyping platforms (e.g., HAPS, VCU118/VPK180-class boards, or custom hardware) for pre-silicon RTL validation and software development
• RTL Implementation: Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock-domain architectures, CDC bridges, and timing closure on dense designs
• IP Integration: Integrate in-house designs with third-party and vendor IP; serve as the expert on the AMD/Xilinx ecosystem (Vivado IP Integrator, transceivers, memory controllers)
• High-Speed Interfaces: Design, implement, and validate high-speed I/O with a focus on PCIe: our accelerators ship as PCIe cards in standard servers
• Post-Silicon Validation: Build FPGA-based "tester" designs for silicon bring-up, device characterization, and automated test environments
• Hardware-Software Stack: Develop the software layer around the hardware: Python/C++ hardware abstraction, register-map generation, and automated build and regression flows
• Lab Debug: Root-cause complex timing and functional issues in real time using ILA/Vivado Analyzer, oscilloscopes, logic analyzers, and BER/eye-diagram characterization of high-speed links

Preferred

• Verification frameworks like Cocotb or UVM
• Experience deploying ML models to FPGAs (hls4ml, FINN, or custom NN-to-RTL flows), or building real-time, sub-microsecond signal processing pipelines
• Mixed-signal ASIC exposure: digital front-ends, ADC/DAC interfaces, or analog compute
• SERDES tuning and signal integrity fundamentals
• CI/CD for hardware (GitLab CI, Docker-based build and test)
• Cocotb
• UVM
• FPGA Deployment
• Machine Learning Models
• hls4ml
• FINN
• NN-to-RTL Flows
• Real-Time Signal Processing
• Sub-Microsecond Pipelines
• Mixed-Signal ASICs
• Digital Front-Ends
• ADC/DAC Interfaces
• Analog Compute
• SERDES Tuning
• Signal Integrity
• Hardware CI/CD
• GitLab CI
• Docker-Based Builds
• Hardware Testing

Benefits

• Hybrid work arrangement

Company

• Applied AI and custom silicon for semiconductors and industrials
• New York, New York, USA
• https://www.normalcomputing.com/
• Founded in 2022
• 51-200 employees

Qualifications

• Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware, ideally in an ASIC prototyping, emulation, or high-growth hardware environment
• Expert-level SystemVerilog and/or VHDL for synthesis, with deep proficiency in Xilinx Vivado (synthesis, place & route, timing closure, IP catalog)
• Hands-on experience implementing and debugging PCIe, plus AXI/AHB, SPI, UART, JTAG, and other common interfaces
• Strong Python for automation, test, and build tooling
• Strong board-level bring-up and lab debugging skills on real hardware
• Startup mindset: you work independently, pivot quickly, and run at ambiguous problems that span hardware, software, and physics
• Verification frameworks like Cocotb or UVM
• Experience deploying ML models to FPGAs (hls4ml, FINN, or custom NN-to-RTL flows), or building real-time, sub-microsecond signal processing pipelines
• Mixed-signal ASIC exposure: digital front-ends, ADC/DAC interfaces, or analog compute
• SERDES tuning and signal integrity fundamentals
• CI/CD for hardware (GitLab CI, Docker-based build and test)

Required skills

• , SystemVerilog, VHDL, Xilinx Vivado, Timing Closure, PCIe, AXI, AHB, SPI, JTAG, Board Bring-Up

Preferred skills

• Verification frameworks like Cocotb or UVM, SERDES tuning and signal integrity fundamentals, CI/CD for hardware (GitLab CI, Docker-based build and test)