Senior ASIC Physical Design Engineer

K2 Space Corporation is building high-power satellite platforms and space systems for commercial and government missions. The company is seeking a Senior ASIC Physical Design Engineer to implement advanced mixed-signal SoCs from synthesis through GDSII, achieve timing closure and PPA optimization, and collaborate with internal teams and external partners. The role also supports physical sign-off, chip integration, tapeout, production, and spaceflight.

Responsibilities

• Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification
• Perform timing closure and optimization across multiple corners and modes using industry-standard tools
• Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence
• Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment
• Develop and maintain scripts and automation to improve flow efficiency and consistency
• Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis
• Assist in chip-level integration, ECOs, and tapeout preparation
• Contribute to methodology development, tool evaluation, and flow documentation
• Support your product through production and spaceflight

Preferred

• Exposure to radiation-hardened or space-qualified ASICs
• Experience with chip-package co-design or advanced packaging (2.5D/3D)
• Familiarity with physical design service vendor management or offshore collaboration
• Experience with sign-off through TSMC
• Experience with Gate-All-Around technologies
• Experience working in cross-functional, geographically distributed teams
• Radiation-hardened ASICs
• Chip-package co-design
• Advanced packaging
• Physical design vendor management
• Offshore collaboration
• TSMC sign-off
• Gate-All-Around technologies
• Collaboration
• Teamwork

Benefits

• Equity in the company
• Paid time off
• Medical coverage
• Dental coverage
• Vision coverage
• Life insurance
• Paid parental leave
• Many other perks

Company

• High-power satellite platforms for Earth-orbit and cislunar missions
• Los Angeles, California, USA
• https://www.k2space.com/
• Founded in 2022
• 51-200 employees

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 5–10 years of experience in ASIC physical design for complex SoCs
• Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent)
• Strong understanding of timing analysis, power optimization, and physical verification flows
• Experience with hierarchical or flat SoC design methodologies
• Familiarity with FinFET technologies
• Working knowledge of DFT, UPF/CPF power intent, and ECO implementation
• Strong problem-solving skills and ability to work cross-functionally in fast-paced environments
• The person hired for this role must therefore either be a “U.S. person” as defined by [22 C.F.R. § 120.15](https://www.law.cornell.edu/cfr/text/22/120.15) or otherwise eligible for a federally issued export control license
• Exposure to radiation-hardened or space-qualified ASICs
• Experience with chip-package co-design or advanced packaging (2.5D/3D)
• Familiarity with physical design service vendor management or offshore collaboration
• Experience with sign-off through TSMC
• Experience with Gate-All-Around technologies
• Experience working in cross-functional, geographically distributed teams
• 5–10 years of experience in ASIC physical design for complex SoCs.

Required skills

• ASIC Physical Design, SoC Design, Synopsys ICC2/Fusion Compiler, Cadence Innovus, Timing Analysis, Power Optimization, Physical Verification, Hierarchical or Flat SoC Design, FinFET Technologies, Design for Test (DFT), UPF/CPF Power Intent, Engineering Change Order (ECO) Implementation, Radiation-Hardened or Space-Qualified ASICs, Chip-Package Co-Design

Preferred skills

• Exposure to radiation-hardened or space-qualified ASICs, Experience with sign-off through TSMC, Experience with Gate-All-Around technologies

Experience

• 5-10 years