ASIC Design Engineer II

Ambarella hires an ASIC Design Engineer II to design and implement processor and memory subsystem components for its AI vision processors. The role includes RTL implementation and optimization, front-end design flow development, chip bring-up and validation, and collaboration with verification teams to address coverage gaps.

Responsibilities

• Design and implement video compression, image processing, vector processing, neural network accelerators, processor cores, and memory subsystems using Verilog and SystemVerilog
• Perform logic design, implementation, and verification utilizing Verilog, SystemVerilog, and relevant programming and scripting languages
• Synthesize and optimize RTL for performance, area, and power efficiency
• Develop and enhance front-end design methodologies and tool flows
• Contribute to chip bring-up and validation efforts
• Analyze code and functional coverage metrics, and collaborate with the verification team to identify and address coverage gaps

Preferred

• Knowledge of logic synthesis and timing closure
• Logic Synthesis
• Timing Closure

Benefits

• Innovative and collaborative environment
• Career development opportunities
• New-hire RSU grants and the opportunity for annual RSU grants

Company

• AI vision processors for edge applications
• Santa Clara, California, USA
• http://ambarella.com/
• Founded in 2004
• 501-1000 employees

Qualifications

• Master's degree in Electrical, Electronics, or Computer Engineering, with 0–5 years of relevant experience
• Solid understanding of computer architecture, logic design, and VLSI design principles
• Proficiency in SystemVerilog, Verilog, and Perl
• Familiarity with design verification methodologies and functional coverage concepts
• Experience with scripting languages and the ability to write assembly language programs
• Strong communication skills and a collaborative, team-oriented mindset
• Demonstrated problem-solving skills and analytical thinking
• Knowledge of logic synthesis and timing closure
• Master’s degree in Electrical, Electronics, or Computer Engineering, with 0–5 years of relevant experience.

Required skills

• SystemVerilog, Verilog, Perl, Computer Architecture, Logic Design, VLSI Design, Design Verification, Functional Coverage, Assembly Language Programming, Logic Synthesis, Timing Closure

Preferred skills

• Knowledge of logic synthesis and timing closure

Experience

• Mid level