Design Verification (DV) Engineer

Hudson River Trading is a technology-driven trading company that develops high-performance compute engines using FPGA and ASIC technology for low-latency trading decisions. The Design Verification Engineer will create verification environments and testbenches for complex HDL, debug RTL designs, manage test infrastructure, and develop internal and open-source tools.

Responsibilities

• Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
• Writing detailed verification plans
• Quickly root-cause RTL bugs
• Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
• Managing test suites and continuous integration infrastructure
• Developing and improving open-source and internal tools

Preferred

• Familiarity with Verilator and/or Cocotb
• C++ experience
• Verilator
• Cocotb
• C++

Benefits

• This role will also be eligible for discretionary performance-based bonuses

Company

• Multi-asset class quantitative trading firm.
• New York, New York, USA
• https://www.hudsonrivertrading.com/
• Founded in 2002
• 1001-5000 employees

Qualifications

• Superb debug and analytical skills
• Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Experience with SystemVerilog and industry-standard frameworks such as UVM
• Experience with Python
• Comfortable in a Linux environment
• A bachelor's degree in computer science, electrical engineering, or a related field
• Familiarity with Verilator and/or Cocotb
• C++ experience

Required skills

• , RTL Functional Verification, FPGA/ASIC Verification, SystemVerilog, UVM, Linux, Code and Functional Coverage Analysis, Verilator, Cocotb

Preferred skills

• Familiarity with Verilator and/or Cocotb, C++ experience

Experience

• 2+ years