Senior ASIC Power Analysis Engineer

PRI Global is seeking a Senior ASIC Power Analysis Engineer for a 12-month remote contract. The role focuses on ASIC power estimation and analysis, PPA optimization, automation of design flows, and supporting power modeling and characterization.

Responsibilities

Set up and maintain PPRTL and PTPX/PrimePower analysis flows for average, time-based, and peak power estimation

Generate and manage activity inputs (FSDB, VCD, and SAIF) from RTL and gate-level simulations, including long-waveform and windowed analysis

Correlate RTL-level power estimates with gate-level signoff power and investigate discrepancies

Generate per-block, per-hierarchy, and per-workload power breakdowns to identify major power contributors, clock power, and datapath inefficiencies

Recommend and evaluate power-reduction opportunities, including clock gating, datapath gating, memory power optimization, idle power, and leakage reduction

Automate power analysis flows and reporting using TCL, Python, and Make-based build systems, integrating them into regression and CI environments

Perform PPA optimization using Synopsys Fusion Compiler

Conduct RTL-level and netlist-level power analysis

Develop scripts to post-process report and log files for format conversion, data analysis, and information extraction

Set up, execute, debug, and analyze reports from ASIC design flows, including synthesis, physical design, power, and timing

Implement selected design blocks at RTL and define power intent using UPF

Support silicon power characterization and power modeling/profiling at the IP and SoC levels

Debug simulation-to-power flow issues end to end

Document methodologies, findings, and recommendations, and communicate results clearly to design teams

Preferred

Hands-on production experience with Synopsys tools, including PPRTL, PTPX/PrimePower, VCS, Verdi, Design Compiler (DC), ICC, and Fusion Compiler (FC), and/or Cadence Joules and PowerArtist

Strong experience with Synopsys PPRTL, PTPX/PrimePower, and Verdi for power analysis and debugging

Experience with low-power design techniques, power analysis tools, and power-intent methodologies, including UPF specifications

Proficiency in TCL, Python, and Excel-based scripting for report processing, model fitting, data visualization, and analysis

Experience working in Linux environments and large-scale compute and job-scheduling environments

Experience with power modeling and profiling at the IP and SoC levels

Ability to troubleshoot end-to-end simulation, synthesis, and power-analysis flows

Synopsys PPRTL

Synopsys PTPX

PrimePower

Synopsys VCS

Synopsys Verdi

Design Compiler

Synopsys ICC

Fusion Compiler

Cadence Joules

PowerArtist

Power Analysis

Power Debugging

Low-Power Design

Power-Intent Methodologies

UPF Specifications

TCL

Python

Excel Scripting

Report Processing

Model Fitting

Data Visualization

Linux

Large-Scale Compute Environments

Job Scheduling

Power Modeling

Power Profiling

IP-Level Power Analysis

SoC-Level Power Analysis

End-to-End Simulation Flows

Synthesis Flows

Power-Analysis Flows

Troubleshooting

Benefits

Remote

Company

IT staffing, managed services, and AI solutions

Wellsville, Missouri, USA

https://priglobal.com/

Founded in 1997

201-500 employees

Qualifications

10+ years of experience as an ASIC Power Engineer, CAD Engineer, or Physical Design Engineer

Experience with power estimation tools, synthesis, and physical design methodologies

Strong understanding of power trade-offs in RTL design and back-end implementation

Hands-on experience with scripting, automation, and data analysis

Bachelor's degree in Electrical Engineering, Computer Science, or an equivalent field/experience

Hands-on production experience with Synopsys tools, including PPRTL, PTPX/PrimePower, VCS, Verdi, Design Compiler (DC), ICC, and Fusion Compiler (FC), and/or Cadence Joules and PowerArtist

Strong experience with Synopsys PPRTL, PTPX/PrimePower, and Verdi for power analysis and debugging

Experience with low-power design techniques, power analysis tools, and power-intent methodologies, including UPF specifications

Proficiency in TCL, Python, and Excel-based scripting for report processing, model fitting, data visualization, and analysis

Experience working in Linux environments and large-scale compute and job-scheduling environments

Experience with power modeling and profiling at the IP and SoC levels

Ability to troubleshoot end-to-end simulation, synthesis, and power-analysis flows

10+ years of experience as an ASIC Power Engineer, CAD Engineer, or Physical Design Engineer.

Required skills

ASIC Power Analysis, PPRTL, PTPX/PrimePower, Verdi, Synopsys Fusion Compiler, Cadence Joules, PowerArtist, UPF, TCL, Python, Low-Power Design, Power Modeling and Profiling

Experience

10+ years