ASIC Power Engineer

Creospan is seeking an ASIC Power Engineer / Physical Design Engineer to perform power analysis and optimization for next-generation AR/VR silicon products. The role focuses on power-analysis flows, identifying and optimizing power bottlenecks, automating analysis, supporting PPA optimization, and implementing RTL/UPF blocks.

Responsibilities

Set up, maintain, and debug RTL- and gate-level power analysis flows using PPRTL and PrimePower/PTPX

Generate and analyze FSDB, VCD, and SAIF activity files; correlate RTL power estimates with gate-level signoff results

Identify power bottlenecks and optimize clock gating, datapath, memory power, and leakage

Automate power analysis, reporting, and data processing using Python, TCL, and Make

Perform PPA optimization using Synopsys Fusion Compiler and support synthesis, physical design, timing, and power analysis flows

Implement RTL/UPF blocks and document power analysis methodologies

Preferred

Experience with Synopsys PPRTL, PrimePower/PTPX, VCS, Verdi, Design Compiler, and Fusion Compiler, or Cadence Joules

Expertise in UPF, low-power design, and power characterization

Strong Python/TCL scripting skills and experience with Linux and large-scale compute environments

Synopsys PPRTL

PrimePower/PTPX

VCS

Verdi

Design Compiler

Fusion Compiler

Cadence Joules

UPF

Low-Power Design

Power Characterization

Python Scripting

TCL Scripting

Linux

Large-Scale Compute Environments

Benefits

Opportunity to learn and apply new skills and methodologies to different clients and industries.

Remote – PST Time Zone

Company

Technology and engineering consultancy for digital modernization and AI

Schaumburg, Illinois, USA

http://creospan.com/

Founded in 1999

201-500 employees

Qualifications

must be able to work in the US without sponsorship now or in the future

10+ years of experience in ASIC power engineering, CAD, or physical design

Hands-on experience with power estimation tools, synthesis, and physical design

Strong understanding of power trade-offs and back-end implementation

Proficiency in scripting, data analysis, and report processing

Bachelor's degree in Electrical Engineering, Computer Science, or equivalent experience

Must be able to work in the US without sponsorship now or in the future

Experience with Synopsys PPRTL, PrimePower/PTPX, VCS, Verdi, Design Compiler, and Fusion Compiler, or Cadence Joules

Expertise in UPF, low-power design, and power characterization

Strong Python/TCL scripting skills and experience with Linux and large-scale compute environments

10+ years of experience in ASIC power engineering, CAD, or physical design.

Required skills

ASIC Power Engineering, Physical Design, Low-Power Design, UPF, Power Characterization, PPRTL, PrimePower/PTPX, VCS, Verdi, Design Compiler, Fusion Compiler, Cadence Joules, Python, TCL, Linux

Experience

10+ years